System architectures with shared memory structures are well known in the art. A shared or global memory space may be accessed by multiple processors or processing elements through a bus or interconnect system. The processing elements are notionally referred to as “bus masters” of the interconnect system, and the shared memory structure resides at the “slave” end. The bus masters make read/write requests to the shared memory resource. The requests are serviced by “memory controllers” at the slave end. In general, the memory controllers complete a point to point connection between a bus master and the common memory space in the interconnect system, in order to facilitate the transfer of data.
It is quite common for multiple bus masters to compete with one another for accessing the shared memory space, since only one access request may be serviceable at any given time. Therefore, access of the shared memory is synchronized such that a bus master is not granted access, while another bus master is being serviced. Scheduling mechanisms or “arbitration schemes” are employed to synchronize and schedule requests from different bus masters in order to avoid contentions. A “bus arbiter” performs the task of arbitration.
A bus arbiter decides which bus master may be granted access to the memory at any given time. When two or more bus masters attempt to access the bus concurrently, only one is granted access, while the other processors must wait. One of the challenges faced by arbiters is ensuring that prioritizing certain bus masters to enable them to access the memory does not cause bus masters with lower priority to get locked out indefinitely or suffer unreasonable delays in gaining access.
A common arbitration scheme is a round robin arbitration scheme, wherein the available bandwidth is allocated evenly among all the bus masters. Memory access is granted according to a predetermined order without regard to latency requirements of individual bus masters. For example, a Digital Signal Processor (DSP) processing voice communications may require low latency communications, but a basic round robin scheme may prove to be very inefficient in accommodating such latency characteristics.
Another well known approach is a token based approach wherein a “token” is passed around the network and only a bus master possessing the token may be allowed access. If a particular processing element does not require access, it may pass the token on to a neighbor. Notions of priority and latency requirements are built into implementations of such schemes. A token based arbitration scheme attempts to guarantee latency requirements by allocating priority based on latency characteristics of the bus masters.
However, these and other well known arbitration schemes do not take into account the transactions at the slave end of the interconnect system. Consider for example, a memory system employing a conventional arbitration scheme. A bus arbiter in the memory system grants access to a first bus master at a particular instance in time. The requested data resides in a first page of the memory, which remains open for the duration of access by the first bus master. Next, a second bus master is granted access. But the second bus master requests data which misses in the first page and a page miss occurs. Considerable delay is incurred in fetching a second page which contains the requested data. Access is then granted to a third bus master that requests data in the first page, and yet another page miss is suffered while the first page is fetched.
In the above example, if the bus arbiter had scheduled the requests differently, such that the first and third transactions, accessing the same page, are scheduled consecutively, it would have resulted in a page hit for the third transaction. But existing techniques are not capable of looking ahead to predict transactions which would result in page hits.
Accordingly, there is a need in the art for techniques wherein memory access latency can be reduced, by taking into consideration the scheduled transactions at the slave end in order to improve page hit rate and balance reads and writes.